memory-controller 开源项目推荐（43 个）

AngeloJacobo /UberDDR3

开源DDR3控制器

someone755 /ddr3-controller

一个用Verilog编写的DDR3（L）PHY和控制器，用于Xilinx 7系列FPGA的应用

Elphel /eddr3

https://git.elphel.com/Elphel/eddr3 之镜

Paradoxdov /memforge

UEFI内存诊断工具——14项压力测试，每芯片卡位映射，MCA捕获，马拉松模式，含DIMM保修信息的明文判决

AngeloJacobo /UberDDR4

Opensource DDR4 Controller

sjo99-kr /DDR-Multi-Channel-Memory-Controller

Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench

krzk /linux

This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).

teekamkhandelwal /SRAM_Controller

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

CMU-SAFARI /Terracotta

A flexible memory control framework to reduce the repeated DRAM interface and controller modifications required by DRAM techniques via custom DRAM command extensions and a programmable memory controller, as described in the MICRO 2026 paper by Songara et al.

FlorianFrank /verilog_baremetal_sram_controller

A bare-metal SRAM memory controller suitable for Xilinx FPGAs.

GhlHub /hyperbus_controller

Xilinx UltraScale+ based HyperBus controller for HyperRam memories

abdo-ehab-euv /sram-controller-uvm-verification

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

yasnakateb /SdramController

🛠 A SDRAM controller in Verilog HDL

SJTU-YONGFU-RESEARCH-GRP /core-ddr2

This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.

SreekashUS /DDR

DDR memory controller implementation and verification

Ashish181104 /Dual-port-ram

Industrial asynchronous dual-port RAM subsystem in Verilog with CDC synchronizers and AXI-style handshake interface.

universal-verification-methodology /core-ddr2

This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.

dysonaicom-svg /hbm-system-model-public

HBM4 System Modeling Platform - High Bandwidth Memory simulation and verification framework

teo1747 /vhdl-zbt-sram-controller

VHDL controller for the Micron MT55L512Y36F ZBT SRAM: single and burst reads and writes, IOBUF data bus, verified against Micron's model

jtsimons /DRAMC

Behavioral architecture of a read/write cycle controller for a DRAM chip.