wyvernSemi /pcievhost
PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities
C155
cosim 话题在 GitHub 上没有填写简介,这里按 Star 数汇总最相关的热门仓库。
PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities
A universal mechanism for implementing Functional Mock-up Units (FMUs) in various languages
Virtual development board for HDL design
Virtio front-end and back-end bridge, implemented with FPGA.
A platform for emulating Virtio devices with FPGAs
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
Co-simulation and behavioural verification with VHDL, C/C++ and Python/m