xilinx-vivado 开源项目推荐（295 个）

ZipCPU /wb2axip

Bus bridges and other odds and ends

suoto /hdl_checker

重新利用现有的HDL工具来帮助编写更好的代码

acageduser /DMA-Attack-Firmware-Customization

本网络安全指南提供了利用LambdaConcept的PCIe Screamer Squirrel DMA板进行硬件混淆的全面方法。该网站仅供教育和研究目的。

ekb0412 /100DaysofRTL

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

derekmulcahy /xvcpi

适用于 Raspberry Pi 的 Xilinx Virtual Cable 服务器

nxbyte /Verilog-Projects

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

ultraembedded /usb2sniffer

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

LightningjovRain /DMA-Attack-rpocket-Firmware-Customization

This cybersecurity guide provides a comprehensive approach to hardware obfuscation using LambdaConcept's PCIe Screamer Squirrel DMA board. It is intended for educational and research purposes only.

pontazaricardo /Verilog_Calculator_Matrix_Multiplication

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

ItzzInfinity /100-days-of-RTL

Trying to get a new skill

Domipheus /ArtyS7-RPU-SoC

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

sailordiary /computer-systems-ucas

中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

rardino /fpga-design-implview

Pictures and an interactive viewer of Vivado implemented designs

splAcharya /DigitalOscilloscope_Zynq7000Soc

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

sarthak268 /Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

siorpaes /BareBonesCortexM0

该项目在 GitHub 上没有填写描述

henrikbrixandersen /elf-bootloader

SPI ELF bootloader for Xilinx Microblaze processors

Kampi /TinyMCU

A RISC-V MCU, written in VHDL, and for learning purposes.

Crimsonninja /senior_design_puf

Repository to store all design and testbench files for Senior Design

Entropify /Entropic_R32-P5_RISC-V

5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, ASIC-flowed, FPGA synthesized