tilelink 开源项目推荐（11 个）

librecores /riscv-sodor

educational microarchitectures for risc-v isa

whutddk /Rift2Core

基于 Chisel3，Rift2Core 是一个 9 级、顺序错序、64 位 RISC-V 核心，支持 RV64GC。

merledu /TileLink

TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

chipsalliance /OmnixtendEndpoint

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

pranav0x2212 /Aetheron

Aetheron is a minimal RISC-V SoC using a TileLink-lite interconnect and basic peripherals that can run bare metal C programs

xuanloc25 /risc_v

Web-based RISC-V (RV32IMF) SoC simulator & assembler — CPU, MMU, cache, TileLink bus, DMA and peripherals, for learning computer architecture.

vyges /tlul-apb-adapter

Generic TL-UL to APB protocol adapter. Connects any APB peripheral to a TileLink Uncached Lightweight (TL-UL) crossbar for Ibex/OpenTitan RISC-V SoCs.

fjpolo /TileLink-Verilog

Formally-verified TileLink modules in Verilog/SystemVerilog

Tape-Out /tilelink

TileLink TL-UL binders for the bus-neutral contracts in hwcore

vyges-ip /tlul-apb-adapter

Generic TL-UL to APB protocol adapter. Connects any APB peripheral to a TileLink Uncached Lightweight (TL-UL) crossbar for Ibex/OpenTitan RISC-V SoCs.

vyges-ip /opentitan-tlul

TL-UL is a lightweight (uncached) bus that combines the point-to-point split-transaction features of the powerful TileLink (or AMBA AXI) 5-channel bus without the high pin-count overhead.