out-of-order 开源项目推荐（44 个）

ucb-bar /chipyard

具有有序核心、无序核心、加速器等的敏捷RISC-V SOC设计框架

RRZE-HPC /OSACA

开源架构代码分析器

mathis-s /SoomRV

A simple superscalar out-of-order RISC-V microprocessor

riscv-software-src /riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

NOP-Processor /NOP-Core

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

sifferman /labs-with-cva6

Advanced Architecture Labs with CVA6

YeXiHuTeam /YeXiHuCore

USTC YeXiHu Team NSCSCC 2026 LA32R out-of-order processor core in Chisel. 中国科学技术大学也西湖队龙芯杯参赛项目。

NoAXI /NoAXI-LoongArch-CPU

Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品

Kingfish404 /raptor-chip

Superscalar OoO RISC-V CPU, marchid: 50 (0x32), RVA22S64/RVI20U32.

bcrafton /processor

A compiler, assembler, and processor.

tommythorn /smolrv64

Advanced 64-bit RISC-V RVA22 4-way issue OoO SoC. Scores 20 in Geekbench 5.4.1 @ 167 MHz

SIMDE-ULL /SIMDE

Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals

devtyagi3909 /riscv-ooo-core

Full superscalar RV32I out-of-order processor with Tomasulos Algorithm, 7-stage pipeline, and UVM testbench. 1st Place + Special Jury Award — SanDisk Hardware Hackathon.

DataSystemsGroupUT /Adaptive-Watermarks

An approach to apply concept drifts and ADWIN on the streams event time to reason about the progress of watermarks

RISMicroDevices /RMM4NC30F2X

Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022

Entropy-xcy /Gem5SimCity

3D WebGL visualization of a gem5 out-of-order CPU core executing a program — PGSimCity for computer architecture. gem5 tracer patch + React/three.js interactive viewer.

RISMicroDevices /RMR8PM3001A

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

etcimon /GSys-LibreCore

A source-available, Linux-capable RISC-V application-class super-processor — and the super-intelligence agentic custom-build platform that carries it from core to silicon through bios and pytorch to any GHz desired.

TawfikYasser /Keyed-Watermarks-in-Apache-Flink

Keyed Watermarks in Apache Flink

noionion /KaiSui

try to design a Single_Emission_Out-of-Order_Pipeline_RISC-V_Processor