chipyard 开源项目推荐（16 个）

ucb-bar /chipyard

具有有序核心、无序核心、加速器等的敏捷RISC-V SOC设计框架

firesim /FireMarshal

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

mit-ll /CEP

通用评估平台（CEP）基于 UCB 的 Chipyard 框架，是一种仅包含无许可证负担、可自由获取组件的 SoC 设计。

etri /omnixtend

Unified open-source repository for OmniXtend protocol implementations in C, Verilog, and Chisel, supporting host and memory roles.

MaxXSoft /Bossa

BOOM's Simulation Accelerator.

RedFlag2017 /rocket-soc-tb

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

ThePituLegend /RISC-V_DE10-Nano

This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.

Fleker /chipyard-viewer

An online viewer for Chipyard output files

yasnakateb /ChipyardIntegration

😱 RoCC Accelerator Integration with Chipyard

NMJ0 /Torch2Gemmini

End-to-end MLIR-based accelerator flow integrating Torch-MLIR, Buddy-MLIR, and Gemmini to compile and run PyTorch workloads on Gemmini accelerator implemented on an FPGA.

anupamsarashwat1-cloud /smvdu-titan-x

A high-performance, production-grade 64-bit RISC-V Multicore SoC ecosystem and industry-standard Cadence ASIC CAD flow (Genus/Innovus). Fully integrated 5-hart coherent core complex, TileLink interconnect, custom RoCC ML Systolic Array, PCIe, USB, HDMI, and silicon-proven IP blocks.

Kian75 /Chisel_Examples

该项目在 GitHub 上没有填写描述

slatte01 /ELEC-H505_Basic-RISC-V-in-order-core-accelerators-and-simple-SoC-generation-ChipYard-

This Github repository serves as a User Guide (UG) for new Chipyard users.

Kleven2k /xorfold-accelerator

Custom RISC-V RoCC accelerator on Chipyard — from register-only compute to autonomous streaming DMA to a real network-checksum algorithm, verified on Rocket and BOOM in Verilator.

Guderlian /model2glass

Automated Pipeline: From Hugging Face AI Models to ASIC GDSII Layouts

R-STEFFES /ChipShop

Web-GUI fuer Chipyard: SoC konfigurieren, Flaeche/Leistung/Yield schaetzen, Verilog bauen