mixed-signal 开源项目推荐（98 个）

open-neuromorphic /awesome-neuromorphic-hw

Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.

SteveLuH /tiadc-mismatch-model

用于 TI-ADC 失配生成、频谱验证和校准基准测试的可复现 MATLAB 行为模型。

JuliaPlots /InspectDR.jl

Fast, interactive Julia/GTK+ plots (+Smith charts +Gtk widget +Cairo-only images)

iic-jku /SKY130_SAR-ADC1

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

manili /VSDBabySoC

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

sgherbst /msdsl

Automatic generation of real number models from analog circuits

curtisseizert /Nanovoltmeter

A low noise nanovoltmeter design files and code

StanfordVLSI /dragonphy2

Open Source PHY v2

gnucap /gnucap

gnucap mirror (read only)

NeuroFan /Algorithmic-SAR-ADC-simulation-files

HSPICE and MATLAB simulation files of a tracking SAR ADC

Arcadia-1 /sar-adc-skills

SAR ADC design knowledge base for agentic IC design: architecture, CDAC, comparator, bootstrap, async logic, integration, and Spectre verification. Includes taped-out 11-bit reference.

MonkHelios /RaspBerry-Pi-High-Altitude-Weather-Balloon-Hardware

Raspberry Pi powered High Altitude Weather Balloon

jonathanhogg /scopething

Pure Python async code for talking to the BitScope micro

Agustin-Delgado /repath

A free, open source, mixed-signal circuit simulator that runs entirely in your browser. Rust engine compiled to WebAssembly, Svelte front end.

michaelklachko /NoisyNet

Code for "Improving Noise Tolerance of Mixed-Signal Neural Networks" https://arxiv.org/abs/1904.01705

VLSIDA /cocotbext-ams

An analog simulator bridge for cocotb — open-source mixed-signal co-simulation

LewisLiuLiuLiu /SerDesSystemCProject

This is a systemC-AMS/systemC SerDes modeling Project

emilitronic /smrct

Sounds like circuit. For small genomic signals

infini8-13 /riscv-ms-soc

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

Joschua-Conrad /Transient-Simulation-of-Dynamic-Comparator-Noise

Verilog-A test block for estimating noise and offset of a dynamic comparator in a transient simulation. Uses the Confidence-Boosting concept published at NEWCAS 2024.