frequency-divider 开源项目推荐（15 个）

anlit75 /ADPLL

全数字锁相环（ADPLL）

arasgungore /VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

arasgungore /256-colors-with-VGA

A VHDL-based VGA driver to display 256 different colors on a monitor.

parasjaing7 /avsdpll_3v3

This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.

emrealci /FPGA-Verilog

Practices related to the fundamental level of the programming language Verilog.

aybaras /VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

Eyantra698Sumanto /VSDOpen_PLL_Tutorial

This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.

adithi-su /fractional-phase-locked-loop

该项目在 GitHub 上没有填写描述

faeze-mhmd /hdl-clock-frequency-divider

Verilog and FPGA implementations of clock generators and a divide-by-113 frequency divider with ModelSim and Quartus results.

Hecate2 /FPGA_miscellaneous

Xilinx Spartan-3E FPGA; taximeter, stopwatch, etc.; verilog

Quanoom /FrequencyDivider

verilog code for frequency divider circuit implemented with verilog hdl

JohnnyLee-master250 /Multicycle-Frequency-Divider

Switch-selectable digital frequency divider improved and integrated from Tsinghua University's Basic Experiments for Electronic Circuits and Systems course.

adamchristiansen /fpga-frequency-doubler

A simple frequency doubler

ilambharathim /pll-5ghz-cmos-integer-n

Transistor-level integer-N PLL targeting ~5 GHz in 90 nm CMOS (GPDK090) - PFD, charge pump, ring VCO, and /48 TSPC divider, simulated in Cadence Spectre

kamberasaf /divide-by-3-clock-divider

SystemVerilog divide-by-3 clock divider with 50% duty cycle using dual counter architecture