cnn-accelerator 开源项目推荐（38 个）

embedeep /Free-TPU

Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.

lirui-shanghaitech /CNN-Accelerator-VLSI

卷积加速器内核，目标ASIC和FPGA

thousrm /universal_NPU-CNN_accelerator

hardware design of universal NPU(CNN accelerator) for various convolution neural network

cea-wind /SimpleTPU

A FPGA Based CNN accelerator, following Google's TPU V1.

user-xleo /DNN-Accelerator

A DNN Accelerator implemented with RTL.

AlexMontgomerie /fpgaconvnet-model

Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.

Jiajun-Ji /CNN_Accelerator

基于Xilinx FPGA的通用型 CNN卷积神经网络加速器，本设计基于KV260板卡，MpSoC架构均可移植

Jiajun-Ji /2023-7th-China-College-IC-Competition-AWCloud-Cup

2023年全国大学生集成电路创新创业大赛-海运捷讯杯-全国二等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition

Kareem-Emad /DCNN-Accelerator

Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.

ansh07verma /fpga-mini-npu

Small-scale FPGA-based Neural Processing Unit (CNN Accelerator) with INT8 systolic array matrix multiplication in Verilog.

msharmavikram /nn_dataflow

Modified version of the "Explore the energy-efficient dataflow scheduling for neural networks. "

tuandam0712 /npu-uvm-verificationNxN

Parameterized NxN systolic-array NPU for signed matrix multiplication, implemented in SystemVerilog RTL and verified using UVM, SVA, directed testing, formal verification, functional coverage, and multi-configuration regression.

fatemekhasraji /FashionMnist_LeNet5

SystemVerilog FPGA acceleration of LeNet-5 CNN for Fashion-MNIST classification, powered by a 5x5 2D Torus Systolic Array with bit-exact Python simulator, and out-of-context Vivado synthesis benchmarks.

ciliweills-glitch /hyperleaf-wheat

Zynq-7000 based hyperspectral PhiPSII edge inference with an INT16 CNN accelerator, AX7020/PYNQ-Z2 deployment and reproducible RTL validation.

L1mozun /tiny-cnn-rtl-accelerator

Synthesizable INT8 CNN accelerator with bit-exact Python/RTL verification and a replaceable MAC interface.

chinmaymahananda /systolic-mac-array

Parameterizable output-stationary INT8 systolic MAC array in Verilog, extended into a weight-stationary 3-layer CNN accelerator (Conv1->Conv2->FC) with interlayer requantization. 20/20 samples bit-exact end-to-end vs a Python golden model; 1,900-case model sweep plus a 206-case constrained-random SV suite. CI on every push.

shri-at /CNNaccelerator

CNN accelerator datapath components

3more102 /lenet5-asic-accelerator

Verified LeNet-5 int8 inference datapath in SystemVerilog, with a bit-exact Python oracle and real sky130hd PPA (pre-layout).

RoshXplore /tiny-yolo-hardware-accelerator

Verilog implementation of a CNN-style image processing pipeline with convolution, activation, pooling, and RTL-based verification.

h23yonsei /fpga-cnn-accelerator-labs

From Verilog to an MNIST CNN accelerator on Spartan-7 / Zynq — line buffers, UART, custom AXI IP, Sobel filtering