clock-divider 开源项目推荐（19 个）

arasgungore /VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

arasgungore /256-colors-with-VGA

A VHDL-based VGA driver to display 256 different colors on a monitor.

JanBurp /MorphaLogic

An eurorack logic module with several logic functions and a clock divider mode. Build around an arduino nano. So could be reprogrammed.

aybaras /VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

suoglu /Verilog-Utilty-Modules

用Verilog编写的实用模块集合

IzyaSoft /EasyHDLLib

A coocbook of HDL (primarily Verilog) modules

HaimOzer123 /Verilog-Clock-Divider-Module---HIT-course---

A Verilog module for generating a divided clock signal with adjustable output frequencies based on a 2-bit input.

joao-carlos-gobatto /miniMIPS

A 32-bit miniMIPS processor implementation in VHDL

dianluniuniu /clock-management-unit

A comprehensive clock management IP core with multiple divider types and glitch-free switching

ramiomer94 /FPGA-DE10Lite-Projects

A A collection of Verilog/SystemVerilog projects developed for the DE10-Lite FPGA board using Intel Quartus.

utkarshad21 /Verilog-HDL-Codes

This repository contains Verilog codes of sequential and combinational circuits along with some protocols.

eli-reid /atmega328p_shiftregister

shift register driver for atmega328p it pushes bits down the line making a pwm or clock divider depending on how you use the shift register outputs

utkarshad21 /Baudrate-Generator

Baudrate Generator (Standard and 16x Oversampling) using Verilog along with Verification

kamberasaf /divide-by-3-clock-divider

SystemVerilog divide-by-3 clock divider with 50% duty cycle using dual counter architecture

Nandhini1009 /full-custom-cmos-clock-divider

Full-custom CMOS programmable clock divider designed and simulated in Cadence Virtuoso.

joao-carlos-gobatto /timed-counter-nexys-4-ddr

A timed counter circuit visualized using the 7 segment displays in Nexys 4 DDR FPGA board.

mlab-modules /CLKDIV01

Multiple division ratios can be selected by jumpers. Possible division ratios are: (÷1, ÷2, ÷4, ÷8) or (÷2, ÷4, ÷8, ÷16) every output is synchronous each other. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state.

yasnakateb /AdaptiveClockManagement

⏳ Adaptive Clock Management in FPGAs Using Binary Search

Vayu-143 /VLSI-Digital-Clock-with-Alarm

Industry-Oriented VLSI Digital Clock with Alarm Functionality implemented in Verilog HDL featuring Clock Divider, BCD Counters, Alarm Controller, RTL Design, Verification Testbench, GTKWave Simulation, and FPGA-Ready Architecture.