180nm 开源项目推荐（16 个）

google /gf180mcu-pdk

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

google /open-source-pdks

Index of the fully open source process design kits (PDKs) maintained by Google.

google /globalfoundries-pdk-libs-gf180mcu_fd_pr

Primitives for GF180MCU provided by GlobalFoundries.

google /globalfoundries-pdks

Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.

google /globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0

7 track standard cells for GF180MCU provided by GlobalFoundries.

rhovector /Cadence_Virtuoso_180nm_Projects

Schematic, Layout Design & Simulation in 180nm Technology

google /globalfoundries-pdk-ip-gf180mcu_fd_ip_sram

SRAM macros created for the GF180MCU provided by GlobalFoundries.

google /globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0

9 track standard cells for GF180MCU provided by GlobalFoundries.

google /globalfoundries-pdk-libs-gf180mcu_fd_io

IO and periphery cells for the GF180MCU provided by GlobalFoundries.

google /globalfoundries-pdk-libs-gf180mcu_fd_bd_sram

SRAM build space for the GF180MCU provided by GlobalFoundries.

google /globalfoundries-pdk-libs-gf180mcu_osu_sc

Digital standard cells for GF180MCU provided by Oklahoma State University.

tejokrishna10 /pll-design-osu-180nm

This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm technology node

erwanregy /TSMC180-Cell-Library

Digital cell library designed in Magic for the TSMC 180nm process, with an accompanying data book generator script

luckyang167-dotcom /two-stage-cmos-opamp-018um

Full-custom 0.18um two-stage CMOS operational amplifier with OpenAccess schematic, layout, DSPF extraction, and demo images

ilambharathim /cdc-mems-microphone-readout

Time-encoded capacitance-to-digital converter (CDC) with switched-capacitor feedback for bias-free MEMS microphone and microfluidic IDE sensor readout - 180 nm CMOS, Cadence Virtuoso

prakhar212005-blip /Low-Power-VLSI-180nm

Low-power CMOS design in TSMC 180 nm (LTspice): pipelined and parallel adders for supply-voltage scaling, a level converter cutting power ~40x, and a 6T SRAM cell.