e-verest

  • 语言Verilog
  • 大小20.3 MB
  • 更新2023年4月12日
在 GitHub 打开
avatarcbalint13
37
50
Apache License 2.0

项目介绍

cbalint13/e-verest 是一个托管在 GitHub 上的开源项目，主要使用 Verilog 编写，采用 Apache License 2.0 许可证，目前获得 37 个 Star、5 次 Fork。

仓库全名
cbalint13/e-verest
开源许可证
Apache License 2.0
Star 数
37
Fork 数
5

README 摘要

e-Versatile Research Stick for peoples Description With the rising of high quality opensource tools for FPGAs new opportunities are emerging to discover and build better digital architectures. This stick is intended as lowest cost tool for anyone who desire to explore & research the world of modern digital systems. It can be used to develop, test and benchmark fairly large digital designs, straight using a complete…

完整内容见 GitHub 原始 README 或本页 。

常见问题

e-verest 用什么语言开发？

主要使用 Verilog 编写，采用 Apache License 2.0 许可证，目前有 37 个 Star。

e-verest 可以免费商用吗？

仓库采用 Apache License 2.0 许可证，可免费使用与修改，商业使用请遵守许可证条款（例如保留版权声明与许可声明）。

如何获取 e-verest 的源码？

可以直接克隆仓库：git clone https://github.com/cbalint13/e-verest.git；安装与运行步骤见仓库 README。

e-verest 最近还在维护吗？

仓库最近一次更新为 2023年4月12日，当前没有未关闭的 Issue；Star 数为 37，可作为社区活跃度的参考。

本页面展示项目元数据与原始 README，GitRead 中文社区 编辑团队负责选题收录。

相关仓库

The-OpenROAD-Project/OpenROAD avatar
OpenROADThe-OpenROAD-Project
1 天前
3.3k
1.1k
239

OpenROAD 的统一应用，实现 RTL 到 GDS 流程。文档见 https://openroad.readthedocs.io/en/latest/

opendb-databaseopenroadlef+7
Verilog
966.6 MB
0
详情
alexforencich/verilog-ethernet avatar
verilog-ethernetalexforencich
2025年2月28日
3.1k
832
116

用于 FPGA 实现的 Verilog 以太网组件

Verilog
5.3 MB
0
详情
darklife/darkriscv avatar
darkriscvdarklife
3 周前
2.6k
331
6

开源 RISC-V CPU 核心，用 Verilog 从零开始在一夜之间实现！

corefpgarisc-v+2
Verilog
4.9 MB
0
详情
corundum/corundum avatar
corundumcorundum
2024年7月5日
2.4k
540
130

开源基于 FPGA 的 NIC 和网内计算平台

fpgain-network-computelinux+2
Verilog
19.9 MB
0
详情
alexforencich/verilog-axi avatar
verilog-axialexforencich
2025年2月28日
2.2k
546
68

用于 FPGA 实现的 Verilog AXI 组件

Verilog
562 KB
0
详情
analogdevicesinc/hdl avatar
hdlanalogdevicesinc
2 天前
2.1k
1.7k
72

HDL 库和项目

analog-devicesfpgahacktoberfest+3
Verilog
146.0 MB
0
详情
pConst/basic_verilog avatar
basic_verilogpConst
3月12日
2.0k
423
0

必备的 Verilog SystemVerilog 模块

alteradebouncedelay+17
Verilog
55.5 MB
0
详情
riscv-mcu/e203_hbirdv2 avatar
e203_hbirdv2riscv-mcu
9月25日
2.0k
432
15

超低功耗 RISC-V 核心

chinacorecpu+9
Verilog
60.6 MB
0
详情

关于

EVEREST: e-Versatile Research Stick for peoples

描述取自 GitHub 官方 API，中文内容由 GitRead 中文社区 编辑团队整理。

简要分析

热度分
84
价值分
27
活跃状态
归档
acceleratorcomputingdspecp5fpgaprocessortensorusbvision
GitHub

语言占比

Assembly
C
Makefile
Python
Verilog

贡献者

cbalint13cbalint13

README

e-Versatile Research Stick for peoples

PCB DIAG

Description

With the rising of high quality opensource tools for FPGAs new opportunities are emerging to discover and build better digital architectures. This stick is intended as lowest cost tool for anyone who desire to explore & research the world of modern digital systems. It can be used to develop, test and benchmark fairly large digital designs, straight using a complete opensource toolchain end to end.

It can close the gap between emerging trend of high level generated systems (automatic reinforced exploration of arhitectures) and the lack of end to end toolchain harvesting a real FPGA for final feedback.

Let Here Be Dragons !

Specs:

  • Small size 16x40mm usb stick
  • Generous 85k LUT FPGA logic space
  • Holds 1Gbyte DDR3 memory with x16 wide access
  • USB3 5Gbps/s data access over x32 wide independent FIFO
  • USB2 outband (same usb port) permanent JTAG and UART independent access
  • Full opensource HDL flow usig YoSYS suite

Can be used in any USB port right from the tips of fingers, no cables, no wires but full control.

OVERVIEW-TOP OVERVIEW-BOTTOM

Progress:

  • 23-Apr-2020 A batch of 50 PCB arrived. Thank you WellPCB PTY LTD !
  • 20-Dec-2020 Second iteraton of PCB has been done, schematics and pcb design are updated.
  • 20-Jan-2021 Announcing OLIMP having e-VEREST as demo board.
  • 17-Aug-2021 Third iteration of PCB has been done, design is updated.
  • 10-May-2022 Due to severe global shortage crowd source batches aren’t possible until >2023.
Booting..
Press ENTER to continue..

     __     _______ ____  _____ ____ _____
   __\ \   / | ____|  _ \| ____/ ___|_   _|
  / _ \ \ / /|  _| | |_) |  _| \___ \ | |
 |  __/\ V / | |___|  _ <| |___ ___) || |
  \___| \_/  |_____|_| \_|_____|____/ |_|

Total BRAM memory: 32 KiB

Select an action:

   [e] Echo UART

Command>

See utils for board peripherial tests and i/o mappings (lpf file).

Project files

  • Open Source Hardware
  • Check schematic available as quick readable document.
  • See the design files available for Altium ®, CircuitMaker ®, KiCAD and Gerber format.
  • There is also an CircuitMaker ® online version available.
  • Software tools for managing the stick and examples coming soon (WiP)
  • There are plans for making batch of units via CrowdSupply campains (WiP).

PCB views

Layer Polygons Description Image
Top Signal Layer Top Layer
Inner 1 GND Plane Inner Layer 1
Inner 2 Signal Layer Inner Layer 2
Inner 3 Power Plane Inner Layer 3 Polygon
Inner 4 GND Plane Inner Layer 4 Polygons
Bottom Signal Layer Bottom Layer Polygon

Credits

评论

暂无评论