sdr-psk-fpga

带FPGA的SDR上的双模PSK收发器

  • 语言Verilog
  • 大小288.1 MB
  • 更新2024年10月10日
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README

Dual-Mode PSK Transceiver on SDR With FPGA

Note 注意

This is a course project of Southeast University (2023 Fall).

Features

  • BPSK/QPSK Modulation
  • Coherent BPSK/QPSK Demodulation
  • Carrier Synchronization (with Costas Loop)
  • Symbol (Timing) Synchronization (with Gardner Loop)
  • Packet-Based Communication
  • Dynamic BPSK and QPSK Switching
  • Pseudorandom (PN) Sequence Generator
  • Block Diagram (with IP + Verilog RTL)
  • Verified with Testbench
  • Tested on SDR
  • Pulse Shaping

You can explore details of implementations in the report.

[!TIP] The current design is resource-efficient. You have plenty of room to implement the remaining features to further enhance the platform.

Platforms

  • SDR: eNodeX 30B
    • FPGA: Xilinx Zynq 7020 (xc7z020clg484-1)
    • 1Tx-1Rx with GSM Antenna (Max 2Tx-2Rx on SDR but we only use 1Tx-1Rx)
    • 4 GPIO as Output Signals (Max 8 GPIO Pins on SDR)
  • Software
    • Vivado 2022.2 (To directly open the project, you need version >= 2022.2)
    • Matlab Filter Designer Toolbox (You can use alternatives to generate Xilinx .coe files)
    • LaTeX (My Version: TeX Live 2023 Latest)
    • Python >= 3.9 (For Data Processing in Report)

Directories

  • behav_sim: Behavioral Simulation Results
  • constraints: Constraints Files
  • ila: Integrated Logic Analyzer (ILA) Results
  • latex: LaTeX Report Source
  • matlab: MATLAB Filter Design
  • schematic: Schematic Diagrams in PDF
  • scopes: Oscilloscope Results
  • scripts: TCL Scripts for Vivado
  • sdr-psk-fpga.*: Vivado Project Directory
  • verilog: Verilog RTL Source
  • waveforms: Waveform Configuration Files

Further Readings

License

This project is distributed under the MIT License. The report is open access under the CC BY-SA 4.0.

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