softcore 开源项目推荐（52 个）

SpinalHDL /VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

WangXuan95 /USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

jamieiles /80x86

80186 compatible SystemVerilog CPU core and FPGA reference design

howerj /forth-cpu

A Forth CPU and System on a Chip, based on the J1, written in VHDL

agra-uni-bremen /microrv32

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

calint /tang-nano-9k--riscv--cache-psram

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

microdynamics-cpu /tree-core-cpu

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Zubax /holoso

Verilog synthesis directly from idiomatic Python for numerical/DSP-heavy applications. Not an HDL.

osresearch /risc8

Mostly AVR compatible FPGA soft-core

calint /tang-nano-20k--riscv--cache-sdram

RISC-V implementation of RV32I for FPGA board Tang Nano 20K utilizing on-board burst SDRAM, flash and SD card

darklife /udarkrisc

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

tommythorn /smolrv64

High performance FPGA-focused 64-bit RISC-V RVA22 4-way issue OoO Soft SoC. Scores 20 in Geekbench 5.4.1 @ 167 MHz

rschlaikjer /fpga-3-softcores

Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

pawlex /hdl.verilog.ipcore.pic.risc16f84

Soft-core uController POC using the risc16f84 pic clone and sdcc c-compiler

aslak3 /cpu

A 16 bit softcore processor implemented in VHDL

devsaurus /t48

A cycle-accurate VHDL model for MCS-48 and UPI devices

renaner123 /TCC

Trabalho de conclusão de curso de título Integração de ramais analógicos com FPGA utilizando processador softcore

aslak3 /cpu32

A RISC/CISC 32 bit softcore processor in VHDL

Zigazou /tang-primer20k-z80

Example Z80-based design for the Tang Primer 20K FPGA board, demonstrating a soft Z80 CPU with USB-to-UART communication.

semahawk /icarium

Trying to implement a soft core SoC