Optimization and inverse design of photonic chips using deep reinforcement learning
semiconductor-devices 开源项目推荐(52 个)
semiconductor-devices 话题在 GitHub 上没有填写简介,这里按 Star 数汇总最相关的热门仓库。
热门项目 前 20
按 Star 数排序展示前 20 个 · GitHub 共 52 个仓库STDF to Wafer Bin Map utility written in Python
Imaging system for analyzing defects of semiconductor wafers and chips
Python program your Job files for an ASML PAS 5500 Stepper Lithography system, by the UCSB Nanofabrication Facility.
QArray - a GPU accelerated constant capacitance simulator for quantum dots
Semiconductor device model, including intermediate band materials and self-consistent optics.
Semiconductor Device Simulator in 2D and 3D
CSC304: Electronic Circuits and Communication Fundamentals [ECCF] & CSL302: Basic Electronics Lab [BE Lab] | SE Semester III | Computer Engineering
Poisson solver for semiconductor hetero-structures
Travelling-Wave-Model (TWM) simulation for a simple semiconductor laser based on the paper "Numerical Study of Dynamical Regimes in a Monolithic Passively Mode-Locked Semiconductor Laser" by A. Vladimirov et al.
Pyhton algorithm for numerical simulation of heterostructure devices
SCAPS-1D simulation of a lead-free FTO/ZnSe/CdTe/Cs2BiAgI6/Ni thin-film solar cell | ten ETLs and nine back contacts screened | 27.99% simulated PCE | figures regenerated from raw exports | Best Poster ACC 2024, 2 granted patents
MEMS patent
This repository contains the Synopsys Sentaurus TCAD project files, scripts, and simulation setup for modeling a Dual Material Gate Junctionless FinFET (DMG-JLFET). The work includes structure creation in Sentaurus Structure Editor, implementation of suitable physical models in the device simulation (sdevice) script, and automation of performance.
Sentaurus TCAD simulation study of 8 nm nanowire Gate-All-Around FETs in Core-Insulator GAAFET (CIGAAFET) configuration along with JUNCTIONLESS FET. Course project for BEVD206L Semiconductor Device Modelling, VIT Chennai (2026).
Scripts to extract model parameters from measurements of a diode.
FPGA-implemented RISC-V processor, evolved from single-cycle to 5-stage pipelined architecture for higher performance and timing efficiency. BRAM-based instruction memory optimizes FPGA usage. Fully FPGA-ready, general-purpose yet tailorable for any AI application, demonstrated with an ML heart rate anomaly detector for wearable AI.
An open-source control library for electrostatically confined spin-qubits developed by HRL Quantum and based on the Quantum Instrumentation Control Kit (QICK).
Contains the mini-project done in the course EE3001
This repository contains easily accessible collection of BSIM-BULK (formerly known as BSIM6) model releases.
关于这个话题
- 清单取自 GitHub 话题页并按 Star 数排序,每次展示前 20 个项目;原始页面见 https://github.com/topics/semiconductor-devices。
- 该话题在 GitHub 上共有 52 个仓库, 本站收录的是其中最热门的 20 个,不是全量列表。
- Star / Fork 每日自动刷新一次,实时数据以 GitHub 为准。
- 当前 20 个项目累计 325 Star,覆盖 5 种主要语言,数据更新于 2026-11-10。
- 中文介绍来自 GitHub 官方话题说明(github/explore)的机器翻译,可点「查看原文」对照;译文缺失时会先展示原文。