rtl-design-and-verification 开源项目推荐（33 个）

MUDAL /Altera_FPGA_Projects

Custom Altera FPGA designs by Olaoluwa Raji. This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA using VHDL.

OrsuVenkataKrishnaiah1235 /RTL-Coding

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

Nidhinchandran47 /DV200

A go-to repository for exploring, learning, and mastering RTL design and verification.

tuandam0712 /npu-uvm-verificationNxN

Parameterized NxN systolic-array NPU for signed matrix multiplication, implemented in SystemVerilog RTL and verified using UVM, SVA, directed testing, formal verification, functional coverage, and multi-configuration regression.

evanneimmoral547 /AtlasRV-32-bit-RISC-V-Pipelined-Processor

Implement a synthesizable 32-bit RISC-V RV32I processor with a 5-stage pipeline, hazard detection, and data forwarding for FPGA verification.

ridash2005 /Hierarchical-Cache-Design

A modular and fully synthesizable 3-level (L1/L2/L3) cache memory subsystem implemented in SystemVerilog, featuring split L1 caches, a centralized L2, and a Last-Level L3 cache with coherence support.

Sanuka-cmd-net /lotus-omni

A Superscalar Out-of-Order RISC-V Processor with Systolic Tensor Acceleration, Structured Sparsity, and a Congestion-Aware Network-on-Chip

paulodietricheng /Top-of-Book-FPGA-Engine

Fully-streaming FPGA Top-of-Book engine with O(log₂N) pipelined arbiter achieving 223.4 MHz on Artix-7.

Hajjy22 /AtlasRV-32-bit-RISC-V-Pipelined-Processor

AtlasRV32 — 32-bit RISC-V pipelined processor with hazard detection and data forwarding, synthesized on Artix-7 FPGA

Khallil973 /RV32I-Core

RV32I 5-Stage Pipelined CPU

Divyanshukumar2005 /4-bit-ALU-with-Status-Flags

4-bit Arithmetic Logic Unit in Verilog with carry-out, overflow and zero flags derived directly from the arithmetic path. Verified with a self-checking testbench targeting flag edge cases, plus gate-level synthesis via Yosys to confirm it's real synthesizable RTL.

Maharishi1313 /LittleProc

RISC-V RV32IM Core

AEjonanonymous /Whittaker-Zero-Invariant

Formal Verification of Whittaker-Type Zero-Invariant Fields and Receiver Symmetry Breaking in Lean 4 and SystemVerilog.

meeeeet /UART-DesignAndVerification

该项目在 GitHub 上没有填写描述

mukund01001 /i2c-uvm-verification

UVM-based verification of an I2C master controller with RTL design, waveform analysis, and Vivado synthesis

divyanshkatiyar /digital-logic-and-vlsi

This specialized engineering repository serves as a production-ready development workspace for synthesizable Register-Transfer Level (RTL) Design and advanced hardware verification architectures utilizing Verilog HDL (IEEE 1364-2005). Decoupled from generic high-level software environments, this repository is explicitly engineered to demonstrate in

HemanjanaKumariKorrapati /Parameterized_Synchronous_FIFO

RTL Design and Verification of a Parameterized Synchronous FIFO in Verilog with directed, corner, and randomized test cases.

Rushikesh-Dandgawhal /Alarm_Clock

Digital Alarm Clock in Verilog HDL | FSM | ModelSim | Intel Quartus Prime | FPGA RTL Design

HemanjanaKumariKorrapati /Parameterized_16-ALU

Parameterized 16-bit ALU designed in Verilog HDL with functional verification, synthesis, RTL schematic, and gate-level netlist.

shrawani0408-boop /Synchronous-FIFO-Verilog-Verification

Designed and verified an 8×8 synchronous FIFO in Verilog with full/empty flag logic using a self-checking testbench, reference model, and randomized test cases.