pipelining 开源项目推荐（157 个）

folbricht /routedns

支持 DoT、DoH、DoQ 和 DTLS 的 DNS 存根解析器、代理和路由器

arm-education /Introduction-to-Computer-Architecture-Education-Kit

用 5 级基于 Arm 的 Verilog 核心和动手实验教授计算机体系结构的教育套件（教育用途）

cross-platform /dspatch

令人耳目一新的简洁跨平台 C++ 数据流 / 补丁 / 流水线 / 图处理 / 流处理 / 响应式编程框架

tugrul512bit /Cekirdekler

Multi-device OpenCL kernel load balancer and pipeliner API for C#. Uses shared-distributed memory model to keep GPUs updated fast while using same kernel on all devices(for simplicity).

taswar /RedisForNetDevelopers

C# samples for the Redis for .NET Developers blog series using StackExchange.Redis: connecting, strings, hashes, lists, sets, sorted sets, HyperLogLog, pub/sub, pipelining, transactions, Lua scripting, geospatial queries and an ASP.NET Core Web API. .NET Framework and .NET Core.

cross-platform /dspatcher

Cross-Platform Graphical Tool for DSPatch

vitorpbarbosa7 /mit_6.004_computation_structures

MIT Course 6.004 - Computation Structures

arn-c0de /ANPS-TradeMeUp

ANPS-TradeMeUp is an LLM-powered AI News Prediction System for short-to-medium term market forecasting, featuring real-time analysis and a Dash-based monitoring dashboard.

ArtemGr /pg_async.rs

Asynchronous, HA (master-master) PostgreSQL driver on top of libpq.

Zubax /holoso

Verilog synthesis directly from idiomatic Python for numerical/DSP-heavy applications. Not an HDL.

princeofpython /Computer-Architecture

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

amoudgl /iir-bandstop-filter

Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic

Effect-Deprecated /query

Efficiently pipeline, batch, and cache requests to any data source

cross-platform /dspatchables

DSPatch Component Repository

nive927 /Flight_Delay_Prediction

A two-stage predictive machine learning engine that forecasts the on-time performance of flights for 15 different airports in the USA based on data collected in 2016 and 2017.

fluidml /fluidml

FluidML is a lightweight framework for developing machine learning pipelines.

yonseicasl /Kite

Kite: Architecture Simulator for RISC-V Instruction Set

djanderson /riscv-5stage-simulator

A 5-stage pipelining RISC-V 32I simulator written in Rust.

stevana /pipelined-state-machines

An experiment in declaratively programming parallel pipelines of state machines.

qossayrida /PipelineProcessorDesign

Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.