microelectronics 开源项目推荐（76 个）

iic-jku /IIC-OSIC-TOOLS

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

RsynTeam /rsyn-x

Rsyn – An Extensible Physical Synthesis Framework

ViennaTools /ViennaPS

微电子制造工艺的地形仿真库

Google-Developers-Sohag /Embedded-Engineering-Portals

A repository for embedded systems learning portals

market-viewer /market-viewer-v1

DIY display for showing current crypto prices

PedroHSCavalcante /uvm-phase-jumping

Simple UVM phase jumping

adrienluitot /analog-course

This is a tutorial to do analog design with open-source resources. It includes installation process, design procedure, layout...

ftorres16 /matchy

A tool for matching devices in analog layout

wwy2020211 /PDA-LSTM

PDA-LSTM: Knowledge-driven page data arrangement based on LSTM for LCM supression in QLC 3D NAND flash memories

ViennaTools /ViennaFit

一个用于将ViennaPS模型与实验数据匹配的Python包。

Islam0mar /Gm_ID_kit.jl

该项目在 GitHub 上没有填写描述

Florin623 /AXI-Lite-Slave-FFT-IP

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

pgolovin /microelectronics

Simple 3D Printer Firmware

MHageH /Interesting_papers

A personal collection of documents usually describing cutting-edge technology and research

litneet64 /tt07-RO-based-PUF

Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)

Silicon-Highway-Technologies /Si-Time

Silicon Highway Technologies Free STA, ASTA Timing Engine

puxina /Open-VLSI

Repository for open-source tools to VLSI design

MatthewWitczak /CMOS-Transimpedance-Amplifier-Design

Design, simulation and full verification of a CMOS transimpedance amplifier.

Florin623 /AXI-Lite-Slave-FPU-IP

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

Florin623 /16-bit-RISC-Pipeline-Processor

4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.