makerchip 开源项目推荐（20 个）

os-fpga /Virtual-FPGA-Lab

This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.

ShonTaware /RISC-V_Core_4_Stage

RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set

AnoushkaTripathi /NASSCOM-RISC-V-based-MYTH-program

Learn digital logic design from basics to pipelines using TL-Verilog and Makerchip — fast, practical, and beginner-friendly! 🚀

ninja3011 /riscv-cpu-core

A pipelined RISC-V CPU Core Implemented in Makerchip using TL-Verilog

ChaminduS /Building-a-RISC-V-CPU-Core

This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.

fjpolo /edXBuildingARISCVCPUCore

edX LinuxFoundationX LFD111x Building a RISC-V CPU Core

RISCV-MYTH-WORKSHOP /riscv-myth-workshop-sep23-fayizferosh

5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD

Eyantra698Sumanto /Digital-Design-on-FPGA

This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.

amitops2103 /verilog-space-commander

An intelligent, Verilog-based AI fleet controller for the Makerchip ASIC Design Showdown 2025. stellar-strike-ai combines predictive targeting, adaptive defense, and boundary-safe maneuvering to dominate in real-time space combat. Designed using TL-Verilog and fully compatible with the Makerchip simulation environment.

xevozen /3bit-PWM-Generator-using-eSim

3bit digitally controlled PWM Generator using eSim, using ngveri(Makerchip) and ngspice

Ashritv /Building-a-RISC-V-CPU-Core

This Repository Contains my TL-Verilog code Developed During Completion of Course Titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX

egimelle /singlecycle-cpu

Single-cycle RV32I CPU core

maazm007 /riscv-myth-core

This repository contains the design of RISC-V CPU 5-staged Core

VishalRoy08 /RISCV-MYTH-Workshop

Five-day RISC-V workshop journey — from ISA fundamentals and ABI to a hand-built, pipelined RV32I CPU core in TL-Verilog.

geekboi777 /RISC-V_CPU_Core

This repository contains the working developer code for a RISC-V_CPU_Core made using TL-Verilog , Makerchip IDE, Sandpiper and Verilator.

vijay080604 /RISC_V_MASTERY

My learning path of understanding of RISC_V with the help VSD System Design

PreethamSK163 /Project-2-RISC-V-CPU-Design-using-TL-Verilog

A hands-on implementation of a RISC-V CPU — progressing from ISA fundamentals and GNU toolchain to a fully functional 5-stage pipelined processor with hazard resolution, bypassing, and memory operations, designed using TL-Verilog on the Makerchip platform.

aagash-joe-lawrence /riscv-myth-workshop

5-stage pipelined RV32I RISC-V CPU written in TL-Verilog and simulated in Makerchip. Covers the RISC-V GNU toolchain and Spike, a single-cycle core, then pipelining with valid-signal control, register bypass, branch/load/jump handling, complete ALU and data memory. RISC-V MYTH Workshop (VSD, Kunal Ghosh, Steve Hoover).

chillakalyan /gsoc-tl-verilog-preparation

Preparation repository for GSoC 2026 (FOSSi Foundation) — Exploring TL-Verilog, Makerchip, and AI-assisted Verilog-to-TLV conversion workflows.

chillakalyan /tlv-virtual-fpga-board

Experimental implementation of Microchip IGLOO Nano FPGA board visualization using TL-Verilog and Makerchip Virtual-FPGA-Lab framework.