hardware-verification 开源项目推荐（190 个）

zhinkgit /embeddedskills

面向Claude Code、Copilot、TRAE和其他支持Skill协议的AI编码助手的开源嵌入式开发和调试技能集合。安装后，人工智能助手可以直接操作编译器、调试器和通信巴士，自动化从代码生成到硬件验证的整个工作流程。

intel /rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

ElNiak /awesome-formal-verification

Welcome to the ultimate list of resources for formal verification techniques and tools. This repository aims to provide an organized collection of high-quality resources to help professionals, researchers, and enthusiasts stay updated and advance their knowledge in the field.

mit-plv /kami

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

gokeshenzhen /TraceWeave

简洁的测试平台日记，波浪（FSDP/BCD），根因分析HCP服务器.一款简单且通用的LCP服务器，通过日志解析和波形分析（FZB/BCD）来应对测试台模拟故障

typetheoryforall /FVjobs

A Job Board for Formal Verification

rpjayaraman /DV-resource

A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.

cristian-mattarei /CoSA

CoreIR Symbolic Analyzer

hanysalah /Design-Pattern-in-SV

This repo is created to include illustrative examples on object oriented design pattern in SV

tmarhguy /alu

8-bit combinational ALU built from scratch with 3,488 CMOS transistors (KiCad + SPICE + Logisim + 1.24M tests

intel /rohd-vf

The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.

kyal102 /chipgate

Deterministic structural sanity checker for Verilog RTL — undriven outputs, multi-driven signals, latch-inference risks, blocking/nonblocking misuse. Pure Python stdlib.

gokeshenzhen /awesome-formal-verification-skill

Open-source, agent-agnostic RTL formal verification skill library for AI coding agents: JasperGold FPV, SVA, proof optimization, and TCL workflows for Claude Code, Codex, Gemini CLI, and Cursor.

rpjayaraman /RTL2UVM

Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.

aebeljs /VeRLPy

VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.

intel /rohd-cosim

Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators

cyril0124 /verilua

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

boldaxolotl /booley

The open-source Agentic Development Environment (ADE) for FPGA/ASIC work

RuihongY /verdi_bridge

Connect AI agents to a live Synopsys Verdi session through MCP: waveforms, signal values, driver tracing, and RTL source.

jetafese /btor2mlir

Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification