verible 开源项目推荐（16 个）

chipsalliance /verible

Verible是一套SystemVerilog开发人员工具，包括解析器、样式linter、格式器和语言服务器

a2k-hanlon /linter-veriloghdl

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

PyFPGA /containers

Containers for FOSS tools

rothej /optical-flow-fpga

Real-time Lucas-Kanade optical flow implemented on FPGA (Nexys A7-100T) for computer vision applications. Uses Python for algorithm verification and benchmarking.

stornado /Open-IC-DEV

Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh，vscode 等开源工具链的开发环境。

capopaul /Public-Verilog-Design-Flow-And-Environment

Provide a basic structure to starts a Verilog or Systemverilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)

aGhandhii /systemverilog-auto-lint-format

SystemVerilog Automatic Linter and Formatter Using Verible Tools

BTA-design-services /tb_lint

TB_LINT - Modular Linting Framework

leandrotozzi /sv-skill

Claude Code skill and svstyle checker for clean, synthesizable SystemVerilog RTL in a lowRISC-derived style

gabrielGAGRA /verilog-2001-lint

Verilog-2001 & FPGA Linter aligned with Google's Verilog Style Guide.

AntonioBerna /vga-pattern-generator

VGA Pattern Generator

opencircuitlabs /hdl-lint-platform

Multi-tool HDL lint orchestration with normalized diagnostics, baselines, policies, and SARIF.

AntonioBerna /kcu105-projects

AMD Kintex™ UltraScale™ FPGA KCU105 Evaluation Kit

stornado /asdf-verible

verible plugin for the asdf version manager.

rothej /fpga-cicd-toolchain-demo

Verible, Verilator, cocotb, and pyuvm CI/CD toolchain demo for 5G NR SystemVerilog RTL.

hw-bzl /rules_verible

Bazel rules for Verible