Must-have verilog systemverilog modules
spi-interface fpga hls encoder delay tcl verilog debounce xilinx synchronizer uart altera uart-verilog fifo pwm uart-protocol spi-master uart-controller uart-tx uart-receiver
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Mar 12, 2026 - Verilog
uart-verilog - 技术专题
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Here are 41 public repositories matching this topic...
A simple, basic, formally verified UART controller
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Jan 29, 2024 - Verilog
A simple implementation of a UART modem in Verilog.
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Nov 10, 2021 - Verilog
Interface Protocol in Verilog
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Aug 2, 2019 - Verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
fpga open-hardware eda digital-logic hardware-designs serialport icestorm uart-verilog iverilog verilog-components uart-interface
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Oct 3, 2025 - Verilog
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
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Sep 27, 2022 - Verilog
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
fpga verilog altera buzzer uart-verilog verilog-hdl 7-segment ir-receiver quartus-prime logifind nec-verilog cyclone-iv ep4ce6e22c8n pl2303 easyfpga
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Sep 10, 2019 - Verilog
☎️ UART Communication Implementation in Verilog HDL
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Mar 22, 2022 - Verilog
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Mar 16, 2019 - Verilog
A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX
fpga uart rs232 uart-verilog serial-communication verilog-library altera-uart fpga-programming serial-communication-fpga fpga-rs232 verilog-rs232 verilog-serial-port verilog-uart
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Aug 6, 2024 - Verilog
Synthesizable Verilog implementation of the classic UART 16550 serial interface implements configurable baud rate, FIFO buffering, parity, error detection, and testbenches for simulation
simulation verilog uart hardware-designs uart-verilog fifo modelsim questasim serial-communication 16550
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Sep 17, 2025 - Verilog
This repository contains the Verilog implementation of a UART protocol with FIFOs for handling data transmission and reception.
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Aug 10, 2025 - Verilog
Universal Asynchronous Receiver Transmitter
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Aug 11, 2020 - Verilog
Verilog Modeling of UART Tx and Rx
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May 5, 2020 - Verilog
An UART implementation. The design is very human
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Feb 22, 2026 - Verilog
Small light-weight implementation of UART in Verilog.
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Dec 20, 2020 - Verilog
Transferring data from SPI to UART using BMP280 sensor with Verilog
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Oct 5, 2024 - Verilog
Displaying images taken from an OV7670/laptop camera
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Dec 15, 2023 - Python
Basys 3 UART Tx for COMPE470L class
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Mar 17, 2019 - Verilog