timing-diagram - 技术专题深度解读

logisim-evolution / logisim-evolution

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

Updated Aug 13, 2026
Java

LudwigCRON / undulate

svg pdf json png waveform eps wavedrom timing-diagram digital-timing-diagrams

Updated Sep 19, 2024
Python

gowthamrajk / UML-Diagrams

In this repository, I will be posting contents to learn about UML diagrams and practical examples for all the UML diagrams which I have designed using Lucid Charts

uml-diagrams uml-state-machine uml-model uml-sequence-diagram communication-diagram uml-class-diagram timing-diagram lucidchart object-diagram interaction-diagram usecase-diagram activity-diagrams package-diagram unified-modeling-language

Updated Sep 3, 2021

jomaway / siggi

siggi creates a signal diagram from text

svg rust education timing-diagram signal-diagram

Updated Mar 14, 2022
Rust

Aniny21 / logi.js

logi.js is a JavaScript library for working with Boolean algebra, logical expressions, truth tables, the Quine-McCluskey algorithm, timing diagrams, and more.

quine-mccluskey boolean-expression boolean-algebra truth-table quine-mccluskey-algorithm logical-operators timing-diagram

Updated Jul 20, 2026
TypeScript

easyeda / eext-timing-diagram-tool

嘉立创EDA专业版扩展：时序图工具 - 基于 WaveDrom 的时序图绘制工具，支持在原理图中创建和放置专业的数字时序图。 EasyEDA proA timing diagram tool based on WaveDrom, supporting creation and placement of professional digital timing diagrams in schematics.

wavedrom timing-diagram easyeda easyeda-extension jlceda jlceda-extension

Updated Jul 30, 2026
JavaScript

IstiakAlin / 4-Bit-ALU-Project

Design a 4-bit ALU capable of performing 4 different arithmetic or logical operations using Quartus, implement it using Verilog HDL, and verify it using a timing diagram.

verilog-hdl timing-diagram arithmetic-logic-unit bit-operations

Updated Jul 17, 2025

Sudhanshu5harma / vlsi

This repository is basic start of building your own processor using verilog (hdl).

register clock verilog mux verilog-hdl arbiter timing-diagram posedge

Updated Jul 25, 2017
Verilog

p-keminer / logic-simulator-studio

Interaktiver Simulator für digitale Logikschaltungen zum Lernen, Planen und weiterentwickeln mit Timing-Analyse, Race-Condition-Erkennung, FSM-Workflows und Verilog-/VHDL-Export. // Interactive digital logic simulator for learning, planing, and further development, with timing analysis, race detection, FSM workflows, and Verilog/VHDL export.

react typescript fsm vhdl verilog digital-logic timing-diagram logic-simulator vite bochum thga digitaltechnik thga-bochum

Updated Mar 25, 2026
TypeScript

timing-diagram - 技术专题

Here are 9 public repositories matching this topic...