static-timing-analysis--sta 开源项目推荐（6 个）

Quang-Minh-Phung /DienTu_TKVM_Documents

该仓库涵盖基础电子学到集成电路设计，重点是前端（RTL/DV）。在电子专业中融入其他职业方向的额外知识。由明宇（蓬光明）编纂。

MohammedS2lah /STA-Visualizer

Interactive Static Timing Analysis (STA) visualizer for understanding Setup & Hold timing with live waveforms, timing diagrams, slack equations, skew, jitter, and path analysis.

smit-1301 /sync-fifo-rtl-to-gdsii

End-to-End ASIC Design of an 8×32 Synchronous FIFO featuring Verilog RTL design, assertion-based verification in Vivado, and RTL-to-GDSII implementation using OpenLane with the SKY130 PDK.

avaamar /eda-analyser

Python tool to automate Quartus STA and synthesis report parsing. Extracts WNS, TNS, and resource utilisation metrics with visual summaries.

Puji7tha /pipelined-cpu-alu-comparator

Two-stage 32-bit pipelined CPU in structural Verilog. Adder architecture comparison through the Cadence/Synopsys flow, plus a tree comparator ALU and the verification gap that let a functional bug through.

kastor-st /kastor-sta

Static timing analyzer in modern C++20: parallel timing propagation, incremental updates and measurable performance.