一种类 C 的硬件描述语言(HDL),将类似高层次综合(HLS)的自动流水线化作为语言构造/编译器特性加入。
hardware-description 开源项目推荐(13 个)
hardware-description 话题在 GitHub 上没有填写简介,这里按 Star 数汇总最相关的热门仓库。
热门项目 全部 13
GitHub 共 13 个仓库,已全部展示Haskell library for hardware description
A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
A Framework for System Modeling, Simulation, and Emulation
Provides a Hardware Description of basics arithmetics on posit format.
32-bit Single-Cycle RISC-V (RV32I) CPU built completely from scratch using basic logic primitives and universal NAND gates in Logisim-Evolution. Features full datapath, ALU, Control Unit, 32-register file, Data Memory, and support for R-type, I-type, S-type, and B-type instructions.
This repository is being used to store the work for my direct RTL neuron implementation that I am creating as part of my research project.
Synthesizable dual-issue out-of-order 64-bit RISC-V processor core with speculative register renaming, non-blocking caches with miss-status holding registers, store-load forwarding, and AXI4 fabric.
Hardware Description (and Simulation) Library
DIG-SYSTEM: A high-performance VHDL DPLL for Xilinx FPGAs. Implements IDELAYE2 primitives with sigma-delta dithering for sub-tap resolution. Features adaptive damping, phase velocity tracking, and robust hysteresis locking. Optimized for precision clock and data alignment.
Structured Machine Readable Datasheet specifications for firmware-relevant hardware facts and AI-assisted embedded development.
🚀 Explore VHDL designs for Year 7 projects, enhancing learning in digital logic through hands-on examples and simulations.
🚀 Design and simulate digital circuits with VHDL using p5.js for interactive visualizations and educational insights.
关于这个话题
- 清单取自 GitHub 话题页并按 Star 数排序,每次展示前 13 个项目;原始页面见 https://github.com/topics/hardware-description。
- 该话题在 GitHub 上共有 13 个仓库, 本站收录的是其中最热门的 13 个,不是全量列表。
- Star / Fork 每日自动刷新一次,实时数据以 GitHub 为准。
- 当前 13 个项目累计 899 Star,覆盖 7 种主要语言,数据更新于 2026-11-08。
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