impulse EDA Playground
Welcome to impulse. This is a playground to learn waveform analysis and protocol verification—start by opening a sample file, explore the starter views, and discover what impulse can do. Sample data includes waveforms from industry formats (VCD, FST, FSDB), transaction-level modeling records, and pin-level protocol analysis with pre-configured views demonstrating hierarchical navigation, transaction extraction, protocol analysis, latency measurement, and compliance checking.
About impulse
impulse is a powerful visualization and analysis workbench designed to help engineers understand, analyze, and debug complex semiconductor and multi-core software systems. It provides seamless integration into IDE frameworks and enables interoperability with a growing set of extensions, such as language IDEs and reporting tools.
impulse is based on a modular framework designed to unify the handling of signal and measurement data from diverse sources. It provides a robust infrastructure for reading, writing, analyzing, and visualizing signals, supporting both simple and highly structured data. impulse’s extensible architecture allows developers to add support for new data formats by implementing custom readers and writers, making it a versatile tool for engineers, scientists, and developers.
Terminology
- Records: Hierarchical containers with scopes and elements (signals, includes, analysis, interfaces).
- Signals: Sequences of samples along a domain (typically time). Supported types include logic, float, integer, enum/event, text, array, struct, and binary.
- Views: Reusable presentations that combine signals, folders, and diagrams (line, gantt, event, charts). Views support multiple axes and cursors. Processing is on demand—only visible parts are computed, and collapsed folders don’t trigger processing.
- Processing & automation: Readers/producers build records; processors and expressions derive or filter signals; value formats and labels control textual rendering.
About EDA
Electronic Design Automation (EDA) refers to the category of software tools used for designing, simulating, and verifying electronic systems such as integrated circuits, FPGAs, and printed circuit boards. This extension specifically focuses on analog circuit simulation, which is essential for analyzing continuous-time and mixed-signal designs. Analog simulation tools such as SPICE (and its variants like HSpice) and SystemC AMS generate simulation data that must be analyzed to verify circuit behavior, performance, and compliance with design specifications.
What’s Here
- 1 waveforms: Industry-standard waveform formats (VCD, FST, FSDB) from RTL simulations with hierarchical scopes and diverse signal types.
- 2 tlm transactions: Transaction-level modeling (TLM) records showcasing AXI, ACE, CHI protocol analysis with SystemC transactions.
- 3 pinlevel transactions: Pin-level protocol analysis combining waveforms with protocol analyzers for AXI4, ACE, and CHI interfaces.
- VCD (Value Change Dump): Industry-standard ASCII waveform format from Verilog/SystemVerilog simulations.
- FST (Fast Signal Trace): Compressed binary format from GTKWave, optimized for large waveforms with fast random access.
- FSDB (Fast Signal Database): Verdi/proprietary format from Synopsys tools, widely used in ASIC verification. Note: Requires valid Synopsys license and FSDB reader library (ffrAPI). See the impulse help system (search for “FSDB Native Reader”) for setup instructions.
- recMz/recMl: impulse compressed/XML record formats containing TLM transaction data with relations and timing.
- recJx: Expression-based records generated on-the-fly via impulse scripts.
- txlog/scv/ftr: Transaction log formats from verification environments (TLM, SystemC, protocol monitors).
Quick Start
- Open any sample file in impulse.
- Click Open Views and pick a matching starter view (see below).
- Need help? Try the impulse videos at https://toem.io/category/resources/impulse-videos/.
Hints
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First Startup: When first time opening impulse, it may take a few seconds to startup the impulse server, especially if you use a slower or loaded external server.
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License Dialog: When opening a view for the first time, you may encounter a license dialog. During the BETA phase, this dialog informs you about the beta status and licensing information. Simply acknowledge the dialog to proceed with exploring the playground samples.
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View Selection: When opening a record, impulse tries to find the best view based on the signals referred to. You can see this judgment in the view selection dialog (Good, Weak, Bad). In some cases, impulse does not find the correct view automatically but opens the view selection dialog for you to select.
License
Our guiding principle for this and all subsequent versions is:
- Non-commercial use is free.
- Commercial use requires a commercial license (including a free plan).
- see LICENSE.md
- see Plans
Documentation & Videos
Enter https://toem.io/resources/ for more information about impulse.
Advanced Features Demonstrated
Protocol Analysis
- Automated transaction extraction: ACE, AXI4, CHI analyzers reconstruct high-level transactions from pin-level signals
- Multi-protocol support: View different protocol layers (TLM base protocol → AXI → ACE/CHI) simultaneously
- Relation tracking: Visualize request-response relationships and transaction dependencies
- Universal format support: VCD, FST, FSDB, and impulse native formats
- Optimized loading: Fast random access to compressed waveforms
- Hierarchical navigation: Deep scope trees with thousands of signals
Analysis Capabilities
- Expression filtering: Filter transactions by protocol fields (e.g., exclude specific commands)
- Statistics extraction: Bandwidth, latency (min/max/median), pending counts
- Charts and metrics: Bar/pie charts for distribution analysis and bandwidth visualization
- Dual cursors/axes: Measure timing differences and compare multiple metrics
Verification Features
- Pin-to-TLM correlation: Bridge pin-level waveforms with transaction-level analysis
- Protocol compliance: Automated checks via protocol analyzers
- Coverage analysis: Transaction distribution and field value coverage
- Debug workflows: Trace protocol violations back to pin-level activity
Prepared Views by Folder
All views include dual cursors (A, B) and dual axes (Primary, Secondary).
Industry-standard digital waveform formats from RTL simulations demonstrating hierarchical navigation, signal grouping, and value analysis.
→ See detailed overview
FSDB Prerequisites: To open FSDB files (3_verilog.fsdb), you need:
- Valid Synopsys VCS or equivalent license
- FSDB reader library (ffrAPI) installed
- Native reader built and configured in impulse
See the impulse help system (search for “FSDB Native Reader”) for detailed setup instructions. VCD and FST samples work without additional prerequisites.
1_arcmodl.vcd → View: arcmodule
- Deep hierarchy navigation (nested scopes) • Multiple signal types (parameters, wires, registers, tri-state) • Folder organization • Logic signal visualization • Chart analysis (bar/pie) for opcode distribution • Expression-based metrics
2_mainft.fst → View: mainft
- Fast Signal Trace (FST) compressed format • Hierarchical scope browsing • Register analysis • Dual cursor/axis support • Efficient large-waveform handling
3_verilog.fsdb → View: verilog
- FSDB format (Synopsys/Verdi) • CPU internals (PC, ALU, registers) • Control flow analysis • Flag tracking (zero, carry) • System-level hierarchies (PCU, ALUB modules)
4_xcomp.fst → View: xcomp
- Clock/reset analysis • Wire/register correlation • Control signal inspection • Mixed signal types
2 tlm transactions
Transaction-Level Modeling records from SystemC verification environments showcasing protocol analysis with timing, relations, and bandwidth metrics.
→ See detailed overview
1_afcdemo.recMz → View: afcdemo
- TLM AXI/ACE-Lite transactions • Non-blocking (nb) and timed variants • PCIe bridge analysis • Transaction relations • Multiple socket monitoring
2_axi4drvx.txlog → View: axi4drvx
- Pin-to-TLM and TLM-to-pin adaptor analysis • Base protocol transactions • AXI protocol layer • Transaction relations visualization • Timed vs. untimed transaction comparison • Bandwidth charts with legends
3_system2.scv → View: system2
- SystemC verification (SCV) format • Router/core complex interaction • Blocking transactions • Initiator/target analysis • Transaction relations
4_xscore71.ftr → View: 4_xscore71
- Multi-protocol analysis (CHI, ACE, AXI4) • Expression filtering (excluding cmd=1) • Transaction statistics (count, pending) • Bandwidth analysis • Memory socket monitoring • Bar charts with multiple members
3 pinlevel transactions
Pin-level waveforms combined with protocol analyzers to extract high-level transaction views from raw signal activity.
→ See detailed overview
1_axiacecomp.fst → View: axiacecomp
- ACE protocol analyzer • Pin-level to transaction extraction • Clock domain analysis • Event signals (ack/req) • Automated transaction reconstruction from waveforms
2_corefs12.recMl → View: corefs12
- ACE interface analysis • RTL wrapper inspection • AXI channels (AW/W/B/AR/R) • Protocol field breakdown (ID, address, size, burst, cache, protection) • Latency statistics (min/max/median) • Bar charts for latency analysis
3_chibull.vcd → View: chibull
- CHI (Coherent Hub Interface) protocol analyzer • Link management signals • Flit-level analysis (request/response/data) • System coherency tracking • IRQ monitoring • Multiple CHI domains
4_axi4test.recJx → View: axi4test
- AXI4 protocol analyzer • Complete AXI4 bus signals (AW/W/B/AR/R channels) • QoS and region support • Lock/cache/protection attributes • Clock/reset monitoring • Comprehensive protocol compliance verification
Explore more impulse features at toem.io
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