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项目介绍

SiEPIC/SiEPIC_EBeam_PDK 是一个托管在 GitHub 上的开源项目,主要使用 Logos 编写,采用 Other 许可证,目前获得 295 个 Star、170 次 Fork。

仓库全名
SiEPIC/SiEPIC_EBeam_PDK
开源许可证
Other
Star 数
295
Fork 数
170
未关闭 Issue
40

README 摘要

SiEPICEBeamPDK SiEPIC EBeam PDK, Library - for silicon photonics layout, design, verification and circuit simulation. This PDK can be used directly for foundry submission, or forked and customized for different purposes (e.g., different thicknesses, different materials). by Lukas Chrostowski ( lukasc-ubc ), (c) 2015-2025, with contributions by: Zeqin Lu , Jaspreet Jhoja , Xu Wang , Jonas Flueckiger , Brett Poulsen (…

完整内容见 GitHub 原始 README 或本页 。

常见问题

SiEPIC_EBeam_PDK 用什么语言开发?

主要使用 Logos 编写,采用 Other 许可证,目前有 295 个 Star。

SiEPIC_EBeam_PDK 可以免费商用吗?

仓库标注的许可证为 Other,商用前请先阅读仓库 LICENSE 文件确认授权范围。

如何获取 SiEPIC_EBeam_PDK 的源码?

可以直接克隆仓库:git clone https://github.com/SiEPIC/SiEPIC_EBeam_PDK.git,默认分支为 master;安装与运行步骤见仓库 README。

SiEPIC_EBeam_PDK 最近还在维护吗?

仓库最近一次更新为 2月14日,当前有 40 个未关闭 Issue;Star 数为 295,可作为社区活跃度的参考。

关于

GitHub 原始描述(英文)

SiEPIC EBeam PDK & Library, for SiEPIC-Tools and KLayout

描述取自 GitHub 官方 API,保持仓库作者书写的原文。

简要分析

热度分
694
价值分
231
活跃状态
活跃

语言占比

Batchfile
Dockerfile
Logos
MATLAB
Python
Shell
XS

Release

README

pypi codecov issues forks Stars

SiEPIC_EBeam_PDK

Download and Installation instructions:

  • Details are provided in the Wiki page: Installation instructions. KLayout’s package manager is used for both downloading and installing the package.

Objectives:

  • Use an open-source layout tool (KLayout) to implement a sophisticated layout design environment for silicon photonics
  • Support for both GUI and script-based layout, or combinations of both.
  • KLayout-INTERCONNECT integration offers a layout-first design methodology. Inspired by Layout Versus Schematic tools, this PDK includes netlist extraction routines to generate a schematic from the layout. This allows the user to directly simulate from the layout, without needing to create the schematic first. This approach is possibly more appealing to photonics designers who are accustomed to designing physical layouts, rather than schematics. A library of components (layout and compact models) is included in the Process Design Kit, specifically for silicon photonics fabrication via Electron Beam Lithography.
  • Whereas a typical schematic-driven design flow includes a schematic, circuit simulation, layout, and verification (see Chapter 10 of the textbook), the approach taken here is Layout-driven, followed by verification, then a schematic (via a netlist extraction) and simulations.
  • Read more details in our two SPIE papers: Design and simulation of silicon photonic schematics and layouts and Schematic Driven Silicon Photonics Design.

Video of a layout and simulation of a ring resonator circuit:

Layout and simulation of a ring resonator circuit

Monte Carlo simulations of a ring resonator circuit, showing fabrication variations:

Monte Carlo simulations of a ring resonator circuit

Layout of a Mach-Zehnder Interferometer:

Layout of a Mach-Zehnder Interferometer

Simulations for the MZI:

Lumerical INTERCONNECT simulations

The SiEPIC-EBeam package includes:

  • Process Design Kit (PDK): this package, including fabrication documentation, scripts, etc.
  • EBeam Layer definitions for KLayout (klayout_Layers_EBeam.lyp).
  • PCells: directional couplers, ring resonator, taper, Bragg grating
  • Sample scripts to create a layout, including waveguide generation functions: Mach-Zehnder Interferometer test structures; Ring resonator test structure.
  • GDS Library, updated with marker layers for verification/netlist generation.

The SiEPIC-Tools package includes:

  • Verification:
    • Scanning the layout. Finding waveguides, devices, pins.
    • Verification: Identifying if there are missing connections, mismatched waveguides, too few points in a bend, etc.
    • Example layouts using the library for verification (EBeam_LukasChrostowski_E_LVS.gds, SiEPIC_EBeam_PDK_Verification_Check.gds).
    • Verification for automated measurements
  • Circuit simulations:
    • Netlist generation
    • Creating a Spice netlist suitable for for circuit simulations. This includes extracting the waveguide length (wg_length) for all waveguides.
    • Menu item “Lumerical INTERCONNECT” will automatically: generate the netlist, launch Lumerical INTERCONNECT to perform the circuit simulations, and pop-up a plot of the transmission spectrum.
    • Monte Carlo simulations, including waveguides, ring resonators built using directional couplers, y-branches, grating couplers.
  • Waveguide functionality:
    • Hot Key “W”: selected paths are first snapped to the nearest pins, then converted to waveguides.
    • Hot Key “Shift-W”: selected waveguides are converted back to paths.
    • Hot Key “Ctrl-Shift-W”: measure the length of the selected waveguides.
    • Hot Key “Ctrl-Shift-R”: resize the waveguides, for a given target length.
  • Layout object snapping
  • Hot Key “Shift-O”: Snaps the selected object to the one where the mouse is hovering over.

Contributing to this project:

You can download the latest development version (master) of the PDK: Zip file download of the PDK

It is posted on GitHub for 1) revision control, 2) so that others can contribute to it, find bugs, 3) easy download of the latest version.

To contribute to the PDK:

  • On the GitHub web page, Fork a copy of the project into your own account.
  • Clone to your Desktop
  • Make edits/contributions. You can use the KLayout IDE to write Python (or Ruby) scripts; KLayout Python IDE for writing/debugging PCells/scripts/macros.
  • “Commit to master” (your own master)
  • Create a Pull Request – this will notify me of your contribution, which I can merge into the main project

I am personally using GitHub desktop to synchronize my files. Then I created symbolic links in my .klayout folder to point to the local copy of this repository. This is useful to automatically update my local KLayout installation (e.g., multiple computers), as changes are made in GitHub.

Screenshots:

Screenshot1 Screenshot2 Screenshot3

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